News: Microelectronics
3 May 2021
JEDEC publishes document for bias temperature instability of SiC MOS devices
The JEDEC Solid State Technology Association (which develops standards for the microelectronics industry) has published ‘JEP184: Guideline for Evaluating Bias Temperature Instability of Silicon Carbide Metal-Oxide-Semiconductor (MOS) Devices for Power Electronic Conversion’. Developed by JEDEC’s JC-70.2 Silicon Carbide Subcommittee, JEP184 is available for free download from the JEDEC website.
JEP184 provides definitions and procedures for characterizing the threshold voltage instability of SiC-based power electronic conversion semiconductor devices having a gate dielectric region biased to turn devices on and off.
Bias temperature instabilities (BTI) involve variations in threshold voltage (VT) and other device parameters such as resistance in the on-state and leakage current in the off-state as a function of the stress time, stress voltage and stress temperature. The assessment of BTI in SiC MOSFETs is particularly challenging since the measured threshold shift can be composed of different components such as long-term VT drift, transient VT changes and hysteresis behavior or changes in hysteresis. The new publication provides guidelines for stress procedures being able to distinguish between different shift components and allowing measurement of their stability over time, as affected by gate bias and temperature.
JEP184 also follows JEDEC’s publication in January of ‘JEP183: Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs’. Together, these two closely related publications provide the industry with guidance on assessing and evaluating BTI variations of VT, as well as accurately measuring the VT of SiC MOSFETs.
“BTI is a frequently requested topic of interest from the automotive and industrial markets adopting SiC power MOSFETs,” notes JC-70.2 subcommittee chair Dr Jeffrey Casady, Wolfspeed Power Die product marketing engineering manager at Cree. “Adding JEP184 to address BTI fills a critical need in this space, and we are grateful to have active participation in JC-70.2 on BTI,” he adds.
“JEDEC’s JC-70 committee is pleased to add JEP184 to its expanding ecosystem of publications,” says JC-70.2 subcommittee vice-chair Dr Peter Friedrichs, vice president SiC at Infineon Technologies. “After releasing the first guideline for SiC specific test procedures (VT) in January (JEP183) we are excited to now start the series of reliability related documents.”
Formed in October 2017 with 23 member companies, JC-70 now has over 60 member companies, underscoring industry commitment to the development of universal standards to help advance the adoption of wide-bandgap (WBG) power technologies. Global multi-national corporations and technology startups from the USA, Europe, Middle East and Asia are working together to bring to the industry a set of standards for reliability, testing and parametrics of WBG power semiconductors. Committee members include industry leaders in power GaN and SiC semiconductors, as well as users of wide-bandgap power devices, and test & measurement equipment suppliers. Technical experts from universities and national labs also provide input.
JEDEC says that interested companies worldwide are welcome to join it to participate in this standardization effort. The next JC-70 committee meeting will be held on 18 May on a virtual platform.
JEDEC WBG Power Semiconductor Committee publishes first guideline for SiC-based devices
JEDEC wide-bandgap power semiconductor committee publishes first document
