17 June 2015

Imec presents post-FinFET research at VLSI Symposium

At the 2015 Symposia on VLSI Technology and Circuits in Kyoto, Japan (15-19 June), nano-electronics research center Imec of Leuven, Belgium has reported new results on nanowire field-effect transistors (FETs) and quantum-well (QW) FinFETs towards post-FinFET multi-gate device solutions.

Imec says that, as most of the industry is adopting FinFETs as the workhorse transistor for the 16nm and 14nm technology nodes, researchers worldwide are looking into the limits of FinFETs and potential device solutions for the 7nm node and beyond. Two approaches, namely silicon gate-all-around nanowire (GAA NW) FETs (which offer significantly better short-channel electrostatics) and quantum-well FinFETs with silicon germanium (SiGe), germanium (Ge) or III-V channels (which achieve high carrier mobility) are promising options. 

Imec says that, for the first time, it has demonstrated integration of these novel device architectures with state-of-the-art technology modules like replacement-metal-gate high-k (RMG-HK) and self (spacer)-aligned double-patterned (SADP) dense fin structures. By building upon existing advanced FinFET technologies, the work shows how post-FinFET devices can emerge, highlighting both new opportunities as well as complexities to overcome, it adds. 

The research into advanced logic scaling is performed in cooperation with Imec's key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Panasonic, Samsung, SK Hynix, Sony and TSMC. Imec and its technology research partners demonstrated SiGe-channel devices with RMG-HK integration. Besides SiGe FinFETs, a unique GAA SiGe nanowire channel formation during the gate-replacement process has been demonstrated. The novel CMOS-compatible process converts fin channels to nanowires by sacrificial Si removal during the transistor gate formation, says Imec. The process may even enable future heterogeneous co-integration of fins and nanowires, as well as Si and SiGe channels. The work also demonstrates that such devices and their unique processing can lead to a drastic 2x or more improvement in reliability (NBTI, negative-bias temperature instability) with respect to Si FinFETs, it is reckoned.

Imec also demonstrated silicon GAA-NW FETs based on silicon-on-insulator (SOI) with RMG-HK. The work compares junction-based and junction-less approaches and the role of gate work-function for multi-Vt (threshold voltage) implementations. New insights into the improved reliability (PBTI, positive-bias temperature instability) with junction-less nanowire devices have been gained, says Imec.

Extending the heterogeneous channel integration beyond Si and SiGe, Imec has demonstrated for the first time, it is claimed, strained Ge quantum-well FinFETs by a novel Si-fin replacement-fin technique integrated with SADP process. Results show that combining a disruptive approach like fin replacement with advanced modules such as SADF-fin, RMG-HK and direct-contacts can enable superior QW FinFETs, Imec says. The devices set the record for published strained Ge pMOS devices, outperforming by at least 40% in drive current at matched off-currents, it is reckoned.

See related items:

Imec demos first strained germanium FinFETs at IEDM

Imec demos first III-V FinFET devices monolithically integrated on 300mm silicon

https://dev.semiconductor-today.com/news_items/2013/NOV/IIMEC_051113.shtml

Tags: IMEC FinFETs III-V CMOS III-Vs-on-Si

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