News

27 August 2009

 

Raytheon awarded $7m Phase 2 COSMOS contract by ONR

The US Office of Naval Research has awarded defense contractor Raytheon Company of Waltham, MA, USA a $7m follow-on Phase 2 contract for work on the Compound Semiconductor Materials on Silicon (COSMOS) program, which is funded by the US Defense Advanced Research Projects Agency (DARPA). Previously, in June, HRL Laboratories LLC of Malibu, CA, USA received an 18-month Phase 2 contract from DARPA and the Air Force Research Laboratory to continue its separate work on COSMOS.

“The COSMOS program focuses on integrating high-performance compound semiconductors, such as indium phosphide or gallium arsenide, with low-cost silicon transistors to achieve superior cost benefits and performance than what is available today,” says Michael Del Checcolo, VP of engineering for Raytheon Integrated Defense Systems (IDS) in Tewksbury, MA. “These technological advances allow us to provide more complex and highly sophisticated solutions,” he adds.

During its $6.5m phase 1 COSMOS contract (awarded in September 2007), the Raytheon-led team demonstrated that high-performance compound semiconductor devices (InP HBTs) can be directly grown and fabricated on silicon substrates and monolithically integrated with silicon CMOS transistors on the same substrate.

Like phase 1, for phase 2 Raytheon IDS is again partnering with Raytheon Systems Ltd in Glenrothes, Scotland, UK; Soitec in Bernin, France; Teledyne Scientific Imaging Company in Thousand Oaks, CA; Massachusetts Institute of Technology in Cambridge, MA; Paradigm Research LLC in Windham, NH; epiwafer foundry IQE's North America manufacturing plant in Bethlehem, PA; and Silicon Valley Technology Center in San Jose, CA (using Raytheon's OpenAIR business model for assembling talent and capabilities).

The phase 2 contract will focus on improving the yield and integration density of compound semiconductor and silicon complementary metal oxide semiconductor (CMOS) transistors fabricated on the same silicon wafer. Specifically, the team will use phase 1’s findings to design and fabricate high-speed, low-power-consumption digital-to-analog converters (DACs) whose performance cannot be realized with existing semiconductor technology.

The COSMOS program’s stated goal of phase 2 is to demonstrate a heterogeneously integrated 13-bit DAC achieving 78dBc of SFDR (spurious-free dynamic range) at 1GHz output frequency. Phase III will be scaled to a much larger circuit, resulting in a heterogeneously integrated 16-bit analog-to-digital converter (ADC) supporting 98dBc of SFDR across a 500MHz bandwidth.

See related items:

IQE commences Phase II of COSMOS

HRL receives Phase II COSMOS contract from DARPA

Raytheon awarded $6.5m for integration of compound semiconductors on CMOS silicon

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Visit: www.darpa.mil/MTO/Programs/cosmos