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The university-research consortium Semiconductor Research Corp (SRC) of Research Triangle Park, NC, USA is funding Scotland’s University of Glasgow in a $2.5m, three-year project ( from 1 January) to identify the best p-channel material to scale minimum MOSFET feature sizes in CMOS devices (including gate length) down to the 8nm technology generation.

By exploiting compound semiconductor materials for the p-type channel, the Glasgow research is expected to enable the shrinking of silicon chips for a further 4-6 years beyond previous projections for the miniaturization roadmap .

Driving the research is the fact that continued scaling of silicon may lead to curbed chip performance. The University of Glasgow will team with SRC to extend silicon’s capabilities, facilitating continued improvements in chip performance while a replacement device is found.

“Being able to utilize MOSFETs in compound semiconductors has been the elusive Holy Grail of scaling for 30 years. With what we expect to accomplish with the University of Glasgow, we may be only 2-3 years away from achieving that breakthrough,” says Dr Jim Hutchby, senior scientist for the Global Research Collaboration (GRC), the unit of the SRC responsible for narrowing the options for carrying CMOS to its ultimate limit. “When the day comes that Moore’s Law scaling of classical silicon CMOS slows, the benefits from our extending the silicon chip using compound semiconductors could be profound for the electronics industry. At that point, we’ll have developed with compound semiconductors a new set of materials and devices to improve both the power dissipation and speed of the historically successful CMOS technology,” he adds.

Switching speeds have increased nearly 20% each year, sustaining Moore’s Law’s aggressive pace of increasing IC functionality. However, the capability to continue this will eventually slow down without the implementation of compound semiconductor materials such as indium gallium arsenide to replace silicon as the channel region of the MOSFET.

To improve carrier velocities, a goal of Glasgow’s work will be to strain p-type compound semiconductors in much the same way that performance enhancements have been realized in silicon. Strained compound semiconductor solutions are expected to yield mobilities of 6,000-50,000cm²/Vs, more than 10 times the values achievable in silicon. This has the potential to significantly reduce switching times, yielding faster chips.

Glasgow will work closely with the Non-Classical Research Center (NCRC), launched in 2006 by SRC-GRC and led by University of California-Santa Barbara. The NCRC is working on providing a sharp increase in carrier velocities in the n-channel. The aim of the new work at Glasgow will be to significantly improve velocities in the p-channel, also using compound semiconductors.

“We’re on our way to proving a new class of compound semiconductors that will provide better peak carrier velocities and lower voltages and allow the industry to supplement silicon’s critical paths for speed and power,” says professor Iain Thayne, project leader for the Glasgow team.

The research will complement and enhance work that the University of Glasgow is already undertaking in this area, supported by the UK Engineering and Physical Sciences Research Council (EPSRC).

Combined with the new research funding at Glasgow, SRC-GRC has committed $10m to non-classical semiconductor advances. With a goal of scaling the CMOS critical dimension (i.e. the gate length) down to 8nm, SRC-GRC conducts what is claimed to be the world’s largest and most comprehensive industry research program for the development of n- and p-type channels using compound semiconductor materials.

Visit: www.src.org

Visit: www.epsrc.ac.uk