NRL awards SUNY Poly $6.25m, five-year grant to use new nanoscale materials to develop electronic devices

The US Naval Research Laboratory (NRL) has awarded $6.25m in federal funding (over five years) to Dr Ji Ung Lee (professor of Nanoscale Engineering) to leverage the 300mm fabrication facility at the Albany campus of State University of New York (SUNY) Polytechnic Institute and use new nanoscale materials to fabricate advanced electronic devices in order to impart more functionalities to future computer chips. Lee’s team will also develop artificial intelligence (AI)-specific hardware, which could lead to greater efficiency for AI applications, such as pattern and voice recognition. The grant represents SUNY Poly’s largest single investigator-faculty award to-date.

The research “could lead to exciting advancements for a variety of both military and public applications that depend on efficient and highly capable electronic hardware,” says SUNY Poly’s interim president Dr Grace Wang.

As part of the NRL award, a number of SUNY Poly graduate students and post-doctoral researchers will be able to take part in the characterization of the materials and devices to be fabricated inside the 300mm cleanrooms. Also, the researchers plan to work closely with an on-site engineering team to be able to fabricate the devices, which will incorporate reconfigurable logic capabilities and 3D monolithic integration technologies to help continue to advance Moore’s Law. Lee will also develop special electronics for the Navy.

The work is a “culmination of ten years of impactful, collaborative research,” says Lee. “With our world-class fabrication capabilities, and together with our experienced SUNY Poly team including dedicated engineers and students, we are fortunate to be leading the way in the development of cutting-edge devices to address NRL and Department of Defense needs,” he adds. “I am also thrilled to provide students with a truly unique experience where they will be able to learn first-hand the skills required to advance technologies in this growing and important field.”

The research ‘SOI Wafer Development and Post CMOS Devices for NRL/DOD requirements’ will include examination of the fundamental properties of materials, leading to the development of novel nanoscale electronic devices to achieve the team’s engineering objectives. Along with the partnering engineering team, Lee’s group plans to fabricate advanced AI-specific hardware to achieve more efficient chips for pattern and image recognition, allowing these applications to be run on handheld devices, in addition to carrying out advanced nanoscale electronic device development in Lee’s laboratory to support the fabrication efforts.

Tags: SOI

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