10 January 2017

University of Illinois-led team develops GaN-on-Si HEMT technology scalable to 200mm substrates

University of Illinois at Urbana-Champaign (UIUC) claims to have recently advanced gallium nitride (GaN)-on-silicon transistor technology by optimizing the composition of the device layers. Working at its Micro + Nanotechnology Lab with industry partners Veeco Instruments Inc of Somerset, NJ and IBM Research Division of Yorktown Heights, NY (with support from the US Air Force Office of Scientific Research), the research team created the high-electron-mobility transistor (HEMT) structure on a 200mm silicon substrate with a process that will scale to larger industry-standard wafer sizes.

According to assistant professor Can Bayram of the Department of Electrical and Computer Engineering (ECE), his team created the GaN HEMT structure on a silicon platform because it is compatible with existing CMOS manufacturing processes and it is less expensive than other substrate options such as sapphire and silicon carbide (SiC).

However, silicon's lattice constant (the space between atoms) does not match up with the atomic structure of the GaN grown on top of it. "When you grow the GaN on top, there's a lot of strain between the layers, so we grew buffer layers [between the silicon and GaN] to help change the lattice constant into the proper size," says ECE undergraduate lead researcher Josh Perozek, lead author of the paper (J Perozek et al 2017 J. Phys. D: Appl. Phys. 50 055103).

Without these buffer layers, cracks or other defects will form in the GaN material, which would prevent the transistor from operating properly. Specifically, these defects — threading dislocations or holes where atoms should be — ruin the properties of the device's two-dimensional electron gas (2DEG) channel, which is critical to the HEMT's ability to conduct current and function at high frequencies.

"The single most important thing for these GaN [HEMT] devices is to have high 2D electron gas concentration," says Bayram about the accumulation of electrons in a channel at the interface between the silicon and the various GaN-based layers above it. "The problem is you have to control the strain balance among all those layers — from substrate all the way up to the channel — so as to maximize the density of the of the conducting electrons in order to get the fastest transistor with the highest possible power density."

Picture: (a) Cross-sectional structure. (b) TEM image of top 80nm of the HEMT structure. The dark gray layer marks the start of the surface. (c) STEM image of top 80nm. The surface starts beneath the black layer and the dark band is the AlN spacer. (d) EDS Chemical Analysis of top 25nm. Data before 4nm are the background values from above the surface.

After studying three different buffer layer configurations, Bayram's team discovered that thicker buffer layers made of graded AlGaN reduce threading dislocation, and stacking those layers reduces stress. With this type of configuration, the team achieved an electron mobility of 1800cm2/V-s.

"The less strain there is on the GaN layer, the higher the mobility will be, which ultimately corresponds to higher transistor operating frequencies," says Hsuan-Ping Lee, an ECE graduate student researcher leading the scaling of the devices for 5G applications.

According to Bayram, the next step for his team is to fabricate fully functional high-frequency GaN HEMTs on a silicon platform for use in the 5G wireless data networks.

When it's fully deployed, the 5G network will enable faster data rates for the world's 8 billion mobile phones, and will provide better connectivity and performance for Internet of Things (IoT) devices and driverless cars.

Tags: GaN-on-Si HEMTs

Visit: http://iopscience.iop.org/article/10.1088/1361-6463/aa5208

Visit: www.mntl.illinois.edu