Leti integrates hybrid III-V silicon lasers on 200mm wafers using standard CMOS process

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7 December 2017

Leti integrates hybrid III-V silicon lasers on 200mm wafers using standard CMOS process

At the 63rd IEEE International Electron Devices Meeting (IEDM 2017) in San Francisco (4-6 December), micro/nanotechnology R&D center CEA-Leti of Grenoble, France has reported the integration of hybrid III-V silicon lasers on 200mm wafers using a standard CMOS process flow. This shows the way to transitioning away from 100mm wafers and a process based on bulk III-V technology that requires contacts with noble metals and lift-off based patterning, Leti says.

Picture: Tilted scanning electron microscopy view of the III-V/Si DFB laser after the III-V patterning steps.

Carried out in the framework of the IRT Nanoelec program (which is headed by Leti), the project demonstrated that the hybrid device’s performance is comparable to the reference device fabricated with the existing process on 100mm wafers. The fabrication flow is fully planar and compatible with large-scale integration on silicon photonic circuits.

CMOS compatibility with silicon photonics lowers fabrication costs and provides access to mature and large-scale facilities, which enables packaging compatibility with CMOS driving circuits, notes Leti.

“Silicon photonic technologies are becoming more mature, but the main limitation of these platforms is the lack of an integrated light source,” says Bertrand Szelag, a co-author of the paper ‘Hybrid III-V/Si DFB Laser Integration on a 200mm Fully CMOS-compatible Silicon Photonics Platform’. “This project showed that a laser can be integrated on a mature silicon photonic platform with a modular approach that does not compromise baseline process performances,” he adds. “We demonstrated that the entire process can be done in a standard CMOS fabrication line with conventional process and materials, and that it is possible to integrate all the photonic building blocks at large scale.”

Picture: Laser spectrum at 160mA injection currents.

The integration required managing a thick silicon film, typically 500nm thick, for the hybrid laser, and a thinner one, typically 300nm, for the baseline silicon photonic platform. This required locally thickening the silicon by adding 200nm of amorphous silicon via a damascene process, which presents the advantage of leaving a flat surface favorable for bonding III-V silicon. The laser can be integrated on a mature silicon photonic platform with a modular approach that does not compromise the baseline process performance.

The novelty of the approach also included using innovative laser electrical contacts that do not contain any noble metals, such as gold. The contacts also prohibit integration lift-off-based processes. Nickel-based metallization was used with an integration technique similar to a CMOS transistor technique, in which tungsten plugs connect the device to the routing metal lines.

The next steps include integrating the laser with active silicon photonic devices, e.g. a modulator and photodiode with several interconnect metal levels in a planarized backend. Finally, III-V die bonding will replace III-V wafer bonding in order to process lasers on the entire silicon wafer.

See related items:

IRT Nanoelec project integrates III-V laser directly on silicon with Mach-Zehnder modulator

Tags: III-Vs-on-Si Direct wafer bonding

Visit: www.leti.fr

Visit: www.irtnanoelec.fr/photonics-on-silicon