9 June 2015

IBM develops technique for co-planar integration of III-V nanoscale devices on silicon

A team at IBM Research's Zurich Research Laboratory in Rüschlikon, Switzerland, with support from the firm's T. J. Watson Research Center in Yorktown Heights, New York, has developed what it says is a relatively simple, robust and versatile process for growing compound semiconductor crystals that will allow them to be monolithically integrated onto silicon wafers – a key step toward making chips that will allow ICs to continue shrinking in size and cost even as they increase in performance (H Schmid et al, 'Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si', Appl. Phys. Lett. 106, 233101 (2015)).

The work could allow an extension to Moore's Law (that the number of transistors on an integrated circuit doubles about every two years). In recent years some have speculated that the ability to keep pace with Moore's Law will become exhausted eventually without new technologies. "We need better performing transistors as we continue down-scaling, and transistors based on silicon won't give us improvements anymore," says Zurich Research Laboratory's Heinz Schmid (the lead author on the paper). The new technique could also impact photonics on silicon, with active photonic components integrated seamlessly with electronics for greater functionality.

The IBM team fabricated single-crystal nanostructures - such as nanowires, nanostructures containing constrictions, and cross-junctions, as well as 3D stacked nanowires - from III–V alloys of indium, gallium and arsenic (InAs, InGaAs, GaAs), which are seen as a possible future material for computer chips, but only if they can be integrated onto silicon. So far efforts at integration have not been very successful, says IBM Research.

The new crystals were grown on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal-organic chemical vapor deposition (MOCVD), which basically starts from a small area and evolves into a much larger, defect-free crystal. This approach allowed them to lithographically define oxide templates and fill them via epitaxy, making nanowires, cross-junctions, nanostructures containing constrictions and 3D stacked nanowires using the already established scaled processes of silicon technology.

SEM images of single-crystal nanostructures fabricated using template-assisted selective epitaxy – silicon is colored in green and III-V material in red. (Images: H Schmid/IBM.)

IBM Research says that the benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple-gate field-effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross-junctions revealed an electron mobility of 5400cm2/V s, while the adjacent InAs MuG-FETs with ten 55nm-wide, 23nm-thick and 390nm-long channels exhibit an on-current of 660μA/μm and a peak transconductance of 1.0mS/μm at VDS =0.5V. These results demonstrate that TASE is a promising fabrication approach for heterogeneous material integration on silicon, the researchers add.

"What sets this work apart from other methods is that the compound semiconductor does not contain detrimental defects, and that the process is fully compatible with current chip fabrication technology," says Schmid. "Importantly, the method is also economically viable."

Schmid adds that more development will be required to achieve the same control over performance in III-V devices that currently exists for silicon. However, the new method is the key to actually integrating the stacked materials on the silicon platform, Schmid says.

Tags: IBM III-Vs-on-Si

Visit: http://scitation.aip.org/content/aip/journal/apl/106/23/10.1063/1.4921962

Visit: www.ibm.com/us/en