22 June 2011

SEMATECH to showcase advanced technologies and manufacturing methods at SEMICON West

Through a wide range of lectures and workshop sessions, global semiconductor manufacturers' research consortium SEMATECH of Albany, NY, USA and International SEMATECH Manufacturing Initiative (ISMI) will present a variety of technology solutions and manufacturing methods at SEMICON West 2011 in San Francisco, CA (11–15 July).

SEMATECH and ISMI will report their latest advances in new materials and device structures and lithography, with a special focus on addressing key opportunities and challenges in 3D interconnect technology. “Both SEMATECH and ISMI recognize that the industry needs innovative and practical solutions for continued scaling of semiconductor technologies that can easily be incorporated into real-world manufacturing environments,” says SEMATECH’s president & CEO Dan Armbrust.

Several SEMATECH experts are scheduled to speak on the SEMICON West TechXPOT Stage, in the North and South Halls of the Moscone Center, including:

• Raj Jammy, VP of Emerging Technologies, on ‘Heterogeneous Integration of High Mobility Ge/III-V Channels on Si’ (12 July at 11am);

• David Gilmer, project engineer of Advanced Memory Technologies, on ‘Metal-Oxide based RRAM Materials and Development’ (12 July at 11:30am);

• Stefan Wurm, associate director of Lithography, on ‘EUV Mask Infrastructure (EMI) Partnership’ (13 July at 11:05am);

• Sitaram Arkalgud, director of Interconnect, will co-moderate the panel session ‘3D in the Deep Submicron Era’ (13 July at 1:50pm); and

• Chris Hobbs, CMOS scaling program manager of Front End Process, on ‘Non-Planar CMOS Device Challenges and Opportunities’ (14 July at the NCCAVS Advanced Process and Integration in Semiconductor Technologies session).

Additionally, SEMATECH and ISMI experts will host and present at various public workshops, at the Marriott Marquis, during SEMICON West:

• Equipment suppliers will identify opportunities and bridge understandings on enabling 3D technology in the wafer handling process space at the workshop ‘Enabling 3D: Temporary Bonding Workshop’ (11 July at 1pm);

• Equipment suppliers and end users will meet to address topics such as SEMI S23 reporting and goals, applying high-temperature process cooling water on process tools, and idle mode interface for process equipment subsystems at the ‘ISMI Equipment Energy Workshop’ (12 July at 8am);
  

• Equipment suppliers will share their plans on how new and existing wafer metrology technologies can be used, modified, or enhanced to measure and improve 3D interconnect processes at SEMATECH’s ‘3D Metrology Workshop’ (13 July at 12:00pm);

• Co-sponsored by SEMI and ISMI, the ‘EDA Workshop’ will focus on the equipment data acquisition (EDA) interface requirements and implementation for the 0710 standards freeze level, with participants able to discuss with industry experts how the changes for the new freeze level can be implemented and evaluated (13 July at 1pm);

• A day-long preview of this year’s International Technology Roadmap for Semiconductors will be offered at the Summer ‘ITRS Public Conference’ (13 July);

• Hosted by SEMATECH, in collaboration with Fraunhofer IZFP, the fifth workshop on ‘Stress Management for 3D ICs using Through Silicon Vias’ will discuss product-level reliability, including product qualification, product-level test requirements, and failure analysis (14 July at 9am).

Tags: SEMATECH

Visit: www.sematech.org

Visit: www.semiconwest.org