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8 December 2011
Intel and IQE present joint papers on III-Vs-on-Si at IEDM
At the 57th annual IEEE International Electron Devices Meeting (IEDM 2011) in Washington DC this week (5-7 December), Intel Corp of Santa Clara, CA, USA and epiwafer foundry and substrate maker IQE plc of Cardiff, Wales, UK have presented three joint papers on recent key developments in compound semiconductor device technologies.
Presented by Intel’s M. Radosavljevic, ‘Electrostatics Improvement in 3-D Tri-gate Over Ultra-Thin Body Planar InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Scaled Gate-to-Drain/Gate-to-Source Separation’ demonstrated for the first time 3D tri-gate indium gallium arsenide (InGaAs) devices with significantly improved electrostatic parameters compared with equivalent ultra-thin-body planar quantum-well field-effect transistor (QW-FETs). The research shows that the 3D tri-gate architecture is an effective way to improve the scalability of III-V FETs for future low-power logic applications.
Presented by Intel’s Gilbert Dewey, ‘Fabrication, Characterization, and Physics of III-V Heterojunction Tunneling Field Effect Transistors (H-TFET) for Steep Sub-Threshold Swing’ demonstrated the steepest subthreshold swing (SS < 60mV/decade) ever reported in a III-V tunneling field-effect transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Overall TFET device performance is improved compared with homojunction TFETs due to the decreased source-to-channel tunnel barrier height.
Presented by Intel’s Niloy Mukherjee, ‘MOVPE III-V Material Growth on Silicon Substrates and its Comparison to MBE for Future High Performance and Low Power Logic Applications’ demonstrated for the first time that the material quality of metal-organic vapour phase epitaxy (MOVPE) III-V quantum-well FET (QW-FET) structures on silicon can be matched to that of the best molecular beam epitaxy (MBE) III-V QWFET structures on silicon, using 75mm-diameter silicon substrates. The research suggests that MOVPE can be a promising technique for III-V material growth on silicon substrates for future logic device applications.
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