News

23 March 2009

 

BMBF grants €8.1m for DECISIF strained silicon project

The German Federal Ministry of Education and Science (BMBF) has granted €8.1m for the project DECISIF (DEvice and CIrcuit performance boosted through SIlicon material Fabrication), which aims to research strained silicon for the manufacturing more powerful and lower-energy-consumption microprocessor and memory chips for portable devices such as laptops, mobile phones and MP3-players.

Total funding of €14.5m includes another €6.4m contributed by the scientific and industrial project partners GLOBALFOUNDRIES Dresden (the joint venture between microprocessor maker AMD and Advanced Technology Investment Company formed earlier this month), silicon wafer maker Siltronic AG, deposition equipment maker Aixtron AG of Aachen, Germany, Research Center Jülich, and the Max Planck Institute of Microstructure Physics. There will also be collaboration with French partners (silicon chip maker STMicroelectronics, silicon-on-insulator substrate maker SOITEC and research center LETI) within the scope of the European Union project MEDEA. The DECISIF project is being coordinated by professor Siegfried Mantl of Research Center Jülich.

A technique patented by the Research Center Jülich will be used, amongst others, to fabricate strained silicon, whereby the crystal lattice of silicon is expanded by mechanical strain to change its electrical properties (so that the charge carriers are able to move significantly faster through the transistor, the potential switching frequency increases and power consumption decreases). This clears the way for more powerful and, at the same time, even smaller transistors. The project aims to combine the properties of (globally) strained silicon with new techniques (involving nano-structuring) to create locally strained silicon, enabling exceptionally high charge carrier mobility within transistors.

DECISIF is intended to build a bridge from fundamental research on strained silicon to almost production-ready process. Combining the new strained silicon and existing silicon-on-insulator techniques aims to develop a new material generation on industry-compatible 300mm wafers, providing the basis for future device technologies and transistors with a minimum geometry of up to 22nm.

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